module sim_ram;
    reg rst;
    reg clk;

    wire [31:0] maddr;
    wire [31:0] mdata;
    wire [31:0] insdata;
    wire [15:0]data_out;
    
    assign data_out = {mdata[31:28], mdata[23:20], mdata[15:12], mdata[7:4]};
    
    PC myPC(
        .reset(rst),
        .clk(clk),
        .next_addr(maddr + 4),
        .insAddr(maddr)
    );
    
    ROM myROM(
        .maddr(maddr),
        .mdata(insdata)
    );
    
    RAM myRAM(
        .maddr(insdata[7:0]),
        .mwdata(32'h123487ab),
        .clk(clk),
        .we(insdata[15]),
        .mm(insdata[15:12]),
        .mdata(mdata)
    );



    initial begin
        // Initialize inputs
        rst = 1;
        clk = 0;

        // Wait for 100 ns
        #20;

        // Release reset
        rst = 0;
     
        #100

        // Finish simulation
        $finish;
    end

    always begin
        #5 clk = ~clk;
    end

    initial begin
        $monitor("clk=%b, rst=%b, mdata=%h, insdata=%h", clk, rst, mdata, insdata[7:0]);
    end
endmodule